Cyrus Tsui
Lattice's Intrepid Leader

Cyrus Tsui doesn’t believe in the “Flanking Attack.” He likes the head-on confrontation, even with an entrenched opponent. He’s not intimidated by numbers or humbled by setbacks. He is a true competitor, and has been in the industry long enough to know that the rules of the game change regularly. This month, Lattice Semiconductor, where Cyrus has been CEO for over 15 years, made its most significant strategic announcement in years, challenging industry leaders head-on in what promises to be one of the most aggressive and lucrative battles of the decade for new market share in programmable logic – the emerging low-cost, high-volume segment.

Lattice has long been respected for its CPLD and PLD offerings, and has made a strong business selling the parts. Cyrus was actually a pioneer in PLDs, working at MMI in the 1970s when the first PAL devices were introduced. “At MMI we were making many different kinds of memories, primarily bipolar PROMs,” says Cyrus. “As we looked at various technologies, we started to investigate AND-OR functions as a way to do math with a PROM. It turned out to be an inherently efficient way to implement logic. We defined an efficient architecture and went looking for customers to prove the concept.”

They found one of their early customers in about 1979 at Data General, on the mini-computer project that was the subject of Tracy Kidder’s Pulitzer-prize-winning book, “The Soul of a New Machine.” MMI marketing took in samples and got the customer excited. The design team then had to deliver the devices for production. “We were aiming for a $5 price, but ultimately we had to charge $50 due to yield problems,” Cyrus recalls. “We also missed our delivery date, and that held up their project. From that experience I learned something that benefited me for the rest of my career. Lattice has never announced a part that it can’t deliver.” [more]

Powering FPGA-based Boards
by John Krehbiel, Intersil

Increased gate counts and higher clock speeds in programmable logic ICs have resulted in higher current requirements while smaller device geometries are driving lower core supply voltages. Simultaneously, new communications and memory technologies (DDR, DDR2) are requiring additional new supply voltages. Table 1 shows this low voltage trend in the generational progression of Xilinx FPGAs (Field Programmable Gate Arrays).

These trends are forcing board designers to utilize more and higher performance power supplies. Fortunately, the latest generation of low voltage power management ICs are keeping pace with the challenges presented by these high-performance boards.

Power Requirements of the Latest Generation of FPGAs

A large part of the value of FPGAs is their flexibility. For example, Altera offers 14 different products in their Stratix/Stratix GX family of FPGAs. These products range in functionality from 10,570 logic elements (LEs) to over 79,000 LEs. (2) In terms of power consumption, the smallest version clocking at less than 100MHz will require less than 1Amp of peak current for the core logic (at 1.5V), whereas the largest version will require almost 14Amps for the core logic when clocked at 300MHz (3). Xilinx’s latest generations of FPGAs are offered in an even wider range of capabilities and power requirements. [more]